In an on-chip regulator used as a power supply circuit supplying electric power to a microcontroller, a memory, and so on, there are requirements such as enabling low power consumption, a Cap-Free system (reduction of terminals, reduction of external components) in which an external capacitance is not attached. However, response properties of a linear regulator depend on a consumption current of a circuit, and therefore, a feedback loop becomes late caused by the lower power consumption, and it is difficult to follow variation of an output voltage. Besides, a variation amount of the output voltage increases resulting that the capacitance is not attached. Accordingly, in the linear regulator, if the low power consumption is enabled and the Cap-Free system is used, the response properties relative to variation of load deteriorate and a lot of time is required until the output voltage is stabled if, for example, the load steeply varies and the output voltage largely changes. As one of methods enabling a linear regulator in which the power consumption is lowered, the Cap-Free system is used, and stable voltage can be supplied, a method in which, for example, a control circuit controlling the output voltage is provided in addition to the feedback loop is proposed as illustrated in FIG. 8 (for example, refer to Patent Document 1).
FIG. 8 is a view illustrating a configuration example of a conventional power supply circuit (linear regulator). The power supply circuit illustrated in FIG. 8 includes an error amplifier 101, an output transistor TR101 using a P-channel transistor, resistances R101, R102, a capacitance C101, an anti-overshoot/undershoot circuit 103, and transistors TR102, TR103. A load 102 is coupled to an output terminal of the power supply circuit. VREF is a constant reference voltage supplied from a not-illustrated reference voltage circuit, VDD is an output voltage of the power supply circuit, VGATE is a voltage supplied to a gate terminal of the output transistor TR101, VFB is a divided voltage generated by dividing the output voltage VDD at the resistances R101, R102 coupled in series.
In the power supply circuit illustrated in FIG. 8, when the divided voltage VFB in accordance with the output voltage VDD becomes lower than the reference voltage VREF, an output voltage of the error amplifier 101 decreases, and the voltage VGATE supplied to the gate of the output transistor TR101 decreases. As a result, an ON-resistance of the output transistor TR101 decreases, and the output voltage VDD increases. On the other hand, when the divided voltage VFB in accordance with the output voltage VDD is higher than the reference voltage VREF, the output voltage of the error amplifier 101 increases, and the voltage VGATE supplied to the gate of the output transistor TR101 increases. As a result, the ON-resistance of the output transistor TR101 increases, and the output voltage VDD decreases. The power supply circuit controls such that a constant voltage is output from the output terminal as the output voltage VDD as stated above.
Here, when a load current Ild to the load 102 varies, the output voltage VDD of the power supply circuit changes resulting from the variation of the load current Ild. For example, as illustrated in FIG. 9, the output voltage VDD of the power supply circuit decreases when the load 102 becomes heavy and the load current Ild steeply increases (time T101). Besides, the output voltage VDD of the power supply circuit increases when the load 102 becomes light and the load current Ild steeply decreases (time T102). To suppress the change of the output voltage resulting from the variation of the load current Ild as stated above, the anti-overshoot/undershoot circuit 103 monitors the output voltage VDD, and performs a control of the transistors TR102, TR103 in accordance with an AC component of the output voltage VDD in the power supply circuit illustrated in FIG. 8.
The anti-overshoot/undershoot circuit 103 suppresses a variation amount by setting the transistor TR102 in on-state (continuity state) to be decrease the output voltage VDD when the output voltage VDD is in an overshoot state. The anti-overshoot/undershoot circuit 103 suppresses the variation amount of the output voltage VDD by setting the transistor TR103 in on-state (continuity state) to decrease the voltage VGATE supplied to the gate of the output transistor TR101 when the output voltage VDD is in an undershoot state. The power supply circuit illustrated in FIG. 8 reduces the overshoot and undershoot of the output voltage VDD resulting from the steep variation of the load current to suppress the variation of the output voltage VDD as stated above.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2010-191885
In the power supply circuit illustrated in FIG. 8, for example, when the load 102 is a memory, the load current Ild is generated when the memory actively operates such as writing of data to the memory and reading of data from the memory. As illustrated in FIG. 10, a case is considered when the writing and so on of data to the memory is repeatedly performed at a period PA, and thereafter, an interval period of times T111 to T112 elapses under a state in which the memory is not operated, then the writing and so on of data to the memory is repeatedly performed again at a period PB from the time T112.
The power supply circuit illustrated in FIG. 8 performs the control of the transistors TR102, TR103 in accordance with only the AC component of the output voltage VDD of the power supply circuit. Accordingly, as illustrated in FIG. 10, the load current Ild is repeatedly generated at the period PA, and thereafter, the load current Ild steeply disappears at the time T111, the output voltage VDD is overshot because a response of the power supply circuit by the feedback loop is late and the control of the output transistor TR101 delays.
If the memory is operated again at the time T112 when the output voltage VDD is overshot and at a high position, the transistor TR103 is in the ON-state (continuity state) to suppress the undershoot of the output voltage VDD resulting from the variation of the load current Ild. The output voltage VDD thereby increases for the same amount as a time when the output voltage VDD is at a steady state though the output voltage VDD of the power supply circuit is at the high position. As a result, the output voltage VDD exceeds an upper limit value Vmax of a power supply voltage range in which the load 102 is able to operate, and there is a possibility in which reliability problems such as operation failure and deterioration of operating life of a product are incurred.
Namely, there is a case when the output voltage VDD is overshot and exceeds the upper limit value Vmax of the power supply voltage range in which the load 102 can operate when the load operation periods in which the load current Ild is repeatedly generated are continuously repeated with a certain time interval in the conventional power supply circuit illustrated in FIG. 8.